Signal Integrity and High Speed Methodology
Course Description
We offer
classes from the beginner to the advanced user. One, two, and
three day classes. Public or private classes at your location.
Have presented classes for over 10 years with excellent real
world examples. No advanced math is required only general
engineering principles. Fast Edges
has taught over 5,000 engineers worldwide - from the USA to
Brazil to South Korea to Japan to Europe.
This class
will allow you to become familiar with signal integrity analysis
at the board level. The lecture's modules address transmission
lines and their effects on digital circuitry and printed circuit
boards. The course will present detailed examples from
real-world designs to demonstrate the necessity of understanding
signal integrity issues and applying sound signal integrity
principles to your PCB Design
With this course you
will gain a better understanding of the following:
• Transmission lines and their effect on
digital circuitry
• Printed circuit boards: drivers, receivers, Zo, Zdiff, stackup
• Quality board designs
• Termination, topology, timing, parasitics, etc
• Crosstalk: understanding and preventing
• Differential pair: termination, routing, timing, EMI
• Clock distribution, high speed busses, groundbounce
• Reference planes: ground, power, return currents, splits
• S parameters
• High speed layout: vias, connectors, capacitors, losses
• Testing issues: equipment, probes, test points
• Models: SPICE, IBIS, drivers, receivers, simulators and
accuracy
• PCB simulations that detect signal integrity problems before
fabrication
• Vias: reference changes, good via design
Audience
• Digital Design Engineers
• ECAD Designers with some high speed experience
• Technicians with High Speed experience
• Those who would like to further their knowledge on Printed
Circuit Board Signal Integrity issues.
• No advanced math is needed
Signal Integrity and High
Speed Methodology
3 - 5 day
class syllabus
What is a transmission line
What causes transmission
lines
What do they do to
digital circuitry
What can be done to avoid
transmission lines
Transmission line effects
Undershoot
Overshoot
Ringback
Monotonicity
Crosstalk
Timing
Overshoot and undershoot
can destroy boards
Reference return current
Where does the return
current flow
How does it flow to the
reference plane
Printed circuit boards
Stackup
How to make controlled Zo
Controlled Zo or
controlled distance
Multiple sources
Drivers, receivers, Zo
How strong should the
drivers be
How fast should the
drivers be
How many receivers can I
have
What should the Zo be
Incident vs reflected
wave switching
Board interconnect delay
How is it different than
system delay
Need to include
interconnect delay in timing
How is it calculated
Receiver input C
Driver output Rs
PCB Zo
Reflected vs incident
wave switching
Termination
When is it needed
Required to stop
undershoot and overshoot
Driver and topology
dependent
Placement and stub length
Parallel
Series
AC parallel
Zo matching
Driver Rs matching
Diode
Topologies
When are topologies
important
How do topologies affect
signal integrity
How do topologies affect
timing
Driver and termination
dependent
Stub length
Short Tee
Long Tee
Star
Daisy chain
Parasitics
L's, C's, and R's
How do they affect the
timing
How do they affect signal
integrity
How to minimize their
effects
How capacitance affects
Zo
Capacitive loading on
transmission lines
Differential pair
Why are they important
Noise and EMI
Layout issues
Zdiff, Zcomm, Zeven, &
Zodd
Controlling Zdiff
Side to side vs broadside
Coupling issues
Weak vs strong coupling
Zdiff changes
Skew affects on timing
Skew affects on signal
integrity
Terminations
Crosstalk
Very important with dense
boards
What causes crosstalk
How can crosstalk be
minimized
What factors can be
controlled
Faster silicon then more
crosstalk
Routing densities
What needs to be done by
layout engineers
Effects on timing
Microstrip vs stripline
Same layer vs dual
stripline
Groundbounce - SSN
What causes groundbounce
What does it do to driver
voltage levels
What does it do to
receiver voltage levels
How can I test for it
How can I stop it
Problems with FPGAs and
ASICs
Number of outputs
switching possible
Bypass capacitors
What physical size
ESL & ESR
Package vs inductance
Placement
PCB electrical mounting
Loop inductance
Reference planes
Perforation
Crossing splits
Consistency in designs
Layer changes
Vias and references
Board to board
consistency
Controls routing
Controls stackup
Connectors
Controlled Zo
Geometry
Pinouts
Reference consistency
Coupling
Vias & plated thru holes
Zo changes
Reference changes
Stub lengths
When are they important
How to avoid vias issues
Blind & buried vias
Dimension affects on
parasitics
Pads, antipads, hole
diameter
S Parameters
Frequency dependent
descriptors
Good for gigahertz
designs
S21 - Insertion loss or
interconnect loss for SI
Includes discontinuities,
connectors, packages
2 & 4 port networks
SnP files
VNA
Quality board designs
What need to done to make
quality boards
What tools are needed to
make quality boards
Signal integrity issues
must be included
AC losses
Skin effect
Dielectric loss
Microstrip vs stripline
Noise margins with
differential pair
Pre-emphasis &
equalization
Layout issues
Boards are becoming more
difficult to layout
What issues are important
in today’s fast boards for layout
PCBs are now part of the
design
Testing issues
Faster boards are harder
to test
How do you test them
What equipment do you
need
How fast does the
equipment need to be
Many older methods no
longer work
IBIS models
Drivers
Receivers
Simulators
Accuracy
Examples (very
detailed):
From paper at European High Speed Symposium in Munich:
Crosstalk
Forward & reverse
Far-end & near-end
Microstrip vs stripline
Driver & receiver
direction affects
Parallel tracking
Spacing
Driver strength & speed
Termination affects
Noise margin
Board layout
Controlling and reducing
How crosstalk changes
timing
Pattern dependent
Problems with multiple
vendors
From paper at User2User High Speed Seminar in San Jose:
Split plane crossings
Reference return current
Signals crossing
reference splits
Microstrip vs Stripline
Size of split
Plane to plane spacing
Timing
Signal integrity
Multiple signals crossing
together
How do splits affect
crosstalk
Vias and reference
changes
Board to board reference
changes
System considerations
